Method and device for testing semiconductor memory devices

ABSTRACT

A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

BACKGROUND

1. Field of the Invention

The invention relates to semiconductor measurements and moreparticularly to a method and a device for the measurement of asemiconductor memory device having a bidirectional data strobe terminalfor a data strobe signal and having at least one data terminal for adata signal at a test apparatus.

2. Background of the Invention

Semiconductor memory devices are tested at test apparatuses whichgenerally have a plurality of identical test heads which each have aplurality of test locations for semiconductor memory devices that are tobe tested (also referred to herein as “devices under test”). Each testlocation has, inter alia, outputs (hereinafter “drivers”), and alsobidirectional inputs and outputs (hereinafter “I/O ports”) foroutputting and for receiving data signals.

The number of I/O ports per test location is limited and, in testapparatuses for conventional semiconductor memory devices, is based onthe number of data terminals of the semiconductor memory devices.Therefore, it is generally a multiple of eight or twelve. Given maximumoccupancy of a test head, all of the I/O ports of a test head areregularly used.

In the course of the test, the data signals output by the test apparatusvia I/O ports transfer data to the device under test, while the datasignals output via data terminals of the device under test transfer datato the test apparatus. In this case, the transfer and the evaluation ofthe data signals received by the test apparatus are always produced in amanner synchronized with an internal clock of the test apparatus.

Semiconductor memory devices of a newer type may also have newerarchitecture that comprises, in addition to the bidirectional dataterminals, at least one further bidirectional terminal for a data strobesignal (data strobe terminal) operated in parallel with the datasignals. The data strobe signal is output (hereinafter also: “driven”)by the semiconductor memory device during the read-out of data from thesemiconductor memory device and by a memory control device (hereinafter“memory controller”) during the writing of data to the semiconductormemory device. Such a signal may serve for controlling or synchronizingwrite and read operations (also termed “data transfer” hereinafter).

During the testing of such semiconductor memory devices of a newer typewhich have a bidirectional data strobe terminal serving forsynchronizing or controlling the data transfer, using a conventionaltest apparatus, that is, one designed for testing conventionalsemiconductor memory devices, problems arise with regard to the numberof available I/O ports per test location and the testing of timeconditions (hereinafter “timing”) of the data strobe signal.

During the read-out of data from the device under test, the testapparatus instigates the read operation and evaluates the data signalspresent at the I/O ports in a manner synchronized to the read operationusing an internal clock of the test apparatus itself. However, if thedevice under test has a data strobe signal of the above-mentioned type,the evaluation of the data signals, in the case of complete testing ortesting close to the application, has to be performed in a mannersynchronized with the data strobe signal, which, in general, does notdepend on the clock signal of the test apparatus. However, testapparatuses designed for conventional semiconductor memory devices arenot designed to measure devices where the clock signal is synchronizedto the device strobe signal.

The second problem relates to the resources of the test apparatus. Themaximum number of possible test locations (and thus also devices undertest) per test head generally results directly from the total number ofI/O ports on a test head and the number of bidirectional terminals on adevice under test. In the case of semiconductor memory devices of aconventional type, only data terminals are regularly bidirectional, andare generally provided in a multiple of eight or twelve in accordancewith the customary data bus width. Accordingly, the total number of I/Oports is also a multiple of eight or twelve. Furthermore, the I/O portsare organized electrically, mechanically and in terms of programming,into units compatible with the data bus width and are limited in termsof their assignability to the test locations.

An additional bidirectional terminal on the semiconductor memory devicereduces the number of devices under test which can be tested in a giventest pass at the test apparatus, since the additionally required I/Oport for the data strobe signal can only be made available by a secondtest location. Since the second test location is then not only blockedfor accommodating a further device under test but, moreover, due to theorganization of the test apparatus, is also unsuitable for makingavailable I/O ports for other devices under test on the common testhead, the number of devices under test per test pass is ultimatelyreduced by half.

In will therefore be appreciated that a need exists to improve testmethods for newer types semiconductor memory devices.

SUMMARY

Embodiments of the present invention provide a test method in which thetiming of an additional data strobe signal is tested in conjunction withdata signals. An exemplary embodiment of the present invention providesa test method for a first semiconductor memory device having abidirectional data strobe terminal used for a data strobe (DQS) signaland at least one bidirectional data terminal used for data signals (DQ).The memory device is connected to at a test apparatus (PA), whichgenerates data strobe and data signals, and transfers and evaluates datasignals. In the course of the test using the data strobe and datasignals, data are transferred from the first semiconductor memory device(P) to a second semiconductor memory device (R) of identical type usedas a reference, and are evaluated after a read-out from the secondsemiconductor memory device (R) by the test apparatus (PA).

Another exemplary embodiment of the present invention includes a testdevice for facilitating testing of a first semiconductor memory devicethat contains a bidirectional data strobe terminal at least onebidirectional data terminal. The test device contains a switching device(SV), which connects the data strobe and data terminals of the first andthe second semiconductor memory device respectively either to a testapparatus or via a respective connection to the corresponding terminalof the respective other semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic illustration of a device according to theinvention in a particularly preferred embodiment.

FIG. 2 shows a schematic timing diagram for signals at a device undertest and a reference during the data transfer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following list of reference symbols is used consistently in thediscussion to follow.

-   -   P Device under test    -   R Reference    -   PA Test apparatus    -   SV Switching device    -   SPDQS Switching unit with respect to DQS at the device under        test    -   SRDQS Switching unit with respect to DQS at the reference    -   SPDQ Switching units with respect to DQ at the device under test    -   SRDQ Switching units with respect to DQ at the reference    -   RK Quiescent contact    -   AK Operating contact    -   SK Switching contact    -   V Delay line    -   t_(Clk) Period duration of the clock signal CLK    -   t_(V) Delay time of the delay line    -   Δt_(DQ) Time offset of DQ at the reference    -   Δt_(DQS) Time offset of DQS at the reference    -   CMD Signals at the control terminals    -   ADR Signals at the address terminals    -   Y Column address of the test data    -   DQ Signal DQ    -   DQS Signal DQS    -   READ Y Control signal for read-out (of the device under test)    -   WRITE Y Control signal for writing (of the reference)

FIG. 1 shows a test apparatus (PA) 2 and two pairs of semiconductormemory devices to be tested, each comprising a device under test (P) 4and a reference (R) 6. In this case, the restriction to two pairsimparts clarity to the illustration. Device under test 4 and reference 6are depicted as DDR-DRAMs in this case. In a preferred embodiment of thepresent invention, the control inputs of the DDR-DRAMs of which CS, RAS,CAS, WE, ADR and CLK are illustrated here, are connected to the driversof the PA, and the seventy two data (DQ) terminals and the data querystrobe (DQS) terminal are connected to a switching device (SV) 8.

SV 8 comprises switching units, in this case relays with quiescent,operating and switching contacts (RK, AK, SK), with each DQ terminal andthe DQS terminal, in each case of device under test 4 and of reference6, connected to the switching contacts SK of the switching units SPDQ,SRDQ, SPDQS and SRDQS, respectively. The quiescent contacts RK of theswitching units SPDQ and SRDQ are connected to I/O ports of the testapparatus PA and the quiescent contacts of the switching units SPDQS andSRDQS are connected to a respective driver of the test apparatus PA. Thecontacts of the relays are depicted in the operating state. Theillustration of the relay driving was dispensed with for reasons ofclarity.

The operating contacts of the switching units SPDQ are connected tothose of the switching units SRDQ, and the operating contact of theswitching unit SPDQS is connected to that of the switching unit SRDQSvia a delay line having the delay time ¼t_(Clk).

During a test, the devices under test 4 and the references 6 are firstlytested in terms of their functionality, as far as possible in the sameway as conventional DRAMs with the switching units SPDQS, SRDQS, SPDQand SRDQ in the quiescent position. This may perfectly well alsocomprise writing to and reading from the DDR-DRAMs. Only the evaluationof DQS during the read-out of the data from the DDR-DRAMs is initiallynot possible.

To that end, a test pattern is written to the devices under test 4 and areference pattern, which can be distinguished therefrom, is written tothe references 6. Afterward, all the switching units in the switchingdevice SV are changed over. As a result, DQS and DQ are isolated fromthe test apparatus and instead respectively corresponding DQ terminalsand the DQS terminals in each case of a device under test 4 and of areference 6 are connected to one another, DQS being delayed betweendevice under test and reference by ¼t_(Clk). Subsequently, a read cycleis initiated on the devices under test and, at a suitable time intervalwith respect thereto, a write cycle is initiated on the references 6,whereupon the test pattern is subsequently transferred from the devicesunder test 4 to the references 6. Subsequently, the connections betweenthe devices under test and the references are disconnected again andinstead the DQS and DQ terminals thereof are connected to the testapparatus.

Finally, the test apparatus reads out the data from the references.Since the latter expect a valid DQS for reading-in data, the testpattern and not the reference pattern is to be read out from them onlywhen the associated device under test 4 has output a valid signal at DQSduring the data transfer.

FIG. 2 shows the sequence of a data transfer from a device under test 4to a reference 6 through illustration of the time profiles of the commonclock signals (CLK, INVCLK), the control, address and DQ signals (CMS,ADR, DQ) and the DQS signal (DQS), in accordance with an embodiment ofthe present invention. In each case the device under test 4 is at thetop and reference 6 at the bottom. A control command READ Y on CMDinstigates the read-out of the data from an address Y on ADR from thedevice under test, and a control command WRITE Y following the nextrising edge at CLK instigates a write operation in the reference. Thetime offset Δt_(DQS) between the DQS at the device under test and theDQS at the reference is about ¼t_(Clk). A small time offset Δt_(DQ)between the DQ at the device under test and the DQ at the referenceresults from a minimum length of the connection between the DQ terminalsof the device under test and of the reference.

The evaluation of the data strobe signal of the first semiconductormemory device (the device under test) is thus left to the secondsemiconductor memory device (the reference). This is possible since eachsemiconductor memory device has the internal elements necessary toevaluate the data and data strobe signals and also their correcttemporal sequence with respect to one another.

Since the data strobe signal is only driven, but not evaluated, by thetest apparatus, the data strobe line no longer has to be connected to anI/O port, but rather can be connected to a simple driver of the testapparatus. Thus, it is possible to test as many semiconductor memorydevices of a new type that contain data strobe lines, as those of aconventional type for a given test pass or test head size.

Thus, the present invention provides improved methods to testsemiconductor devices of a new type, including those with data strobeterminals. The semiconductor memory device of a new type that is to betested (the device under test) is connected to the test apparatus fortesting semiconductor memory devices of the conventional type at a testlocation like such an otherwise identical semiconductor memory device ofa conventional type, the bidirectional data strobe terminal of thedevice under test being connected to a driver of the same test locationdirectly or via a switching device controlled by the test apparatus. Thedevice under test is then subjected to a test sequence corresponding tothat for semiconductor memory devices of a conventional type, duringwhich the test apparatus generates the data strobe signal via the driverduring the writing of data in a suitable manner.

After the first part of the test sequence, the device under test iscompletely tested apart from the evaluation of the data strobe signalduring the read-out of data from the device under test.

In order to test the data strobe signal during the read-out of data fromthe device under test with regard to valid signal levels and temporalposition with respect to the data signals, the procedure is as follows:

Test data are written to the device under test to at least one test dataaddress, and reference data which can be distinguished from the testdata are written to the reference at the test data address. The data anddata strobe terminals of the device under test and of the reference arethen disconnected from the test apparatus and connected to one anotherinstead by means of a switching device controlled by the test apparatus.Subsequently, the test apparatus initiates firstly a read operation atthe device under test and, at a suitable time interval—prescribed by thetiming specifications of the semiconductor memory device—following theread operation, a write operation at the reference, that is to say, adata transfer of the test data from the device under test to thereference at the test data address of the test and reference data. Afterthe data transfer, the data terminals of the reference are disconnectedfrom the device under test and are connected to the test apparatus. Thetest apparatus then reads out the data at the test data address.

The test data can be read out from the reference only when a correctdata strobe signal has been driven by the device under test during thedata transfer from the device under test to the reference. Otherwise,the unchanged reference data are read out from the reference.

The data strobe and data lines are changed over by means of switchingdevices (e.g., relays, FETs) controlled by the test apparatus.

A previously tested semiconductor memory device of the same type that iscontained in the abovementioned switching device may respectively beused as a reference for each device under test. In this case, thereference is a constituent part of the switching device and remains sowhile new devices under test are always mounted at the test location fortest purposes. Surplus drivers of the test location are used for drivingthe reference, while the I/O ports of the test location are alternatelyconnected to the device under test or to the reference.

Preferably, however, a second device under test on the same testapparatus, particularly preferably on the same test head, is used as thereference. In the case where the test head is occupied by an even numberof devices under test, the devices under test are divided into twogroups, PG and RG. Firstly, the devices under test in the group PG aretested with the devices under test in the group RG used as reference.Thereafter, the devices under test in the group RG are tested with thosein the group PG used as reference.

The test method according to embodiments of the present invention canparticularly preferably be applied to semiconductor memory devices witha double data rate interface (DDR-IF) in accordance with a JEDECstandard. The DDR interface is customarily employed nowadays,particularly on DRAMs.

In contrast to conventional synchronous semiconductor memory devices, inwhich write and read accesses take place in each case at the rising orfalling edge of a clock signal, in semiconductor memory devices withDDR-IF a data transfer is possible both upon the rising and upon thefalling edge of the clock signal, thus resulting in an approximatedoubling of the possible data transfer rate for a given clock frequency.However, rather than the clock signal (CLK), a “data query strobe” (DQS)signal derived therefrom is used for the synchronization of the actualdata transfer between semiconductor devices with DDR-IF. DQS correspondsto a data strobe signal which is generated by the semiconductor memorydevice during the reading of data from a semiconductor memory devicelike the data signals, and by a memory controller during the writing ofdata to the semiconductor memory device like the data signals.

During the writing of data to the semiconductor memory device withDDR-IF, DQS is controlled in such a way that each edge of DQS indicatesthe center of a transferred data bit at DQ. The semiconductor memorydevice with DDR-IF accepts the data on DQ in each case at the instant ofan edge at DQS.

During reading from the DDR-IF semiconductor memory device, DQS isgenerated edge-synchronously with the data DQ. The memory controllerexpects the data on the data lines after each edge at DQS.

Thus, it is necessary to unambiguously define the propagation times ofDQ and DQS during the data transfer between device under test andreference by means of delay devices, in order to actually enable acorrect data transfer in the first place or to test the timing betweenDQ and DQS with regard to a sufficient margin.

Monostable multivibrators, bucket-brigade devices or delay lines aretaken into consideration as delay devices.

The connecting line between the DQS terminal of the device under testand that of the reference may contain further devices which serve totest the DQS signal under intensified conditions, for instance through alowering of the signal level of DQS.

Equally, it is possible to equip the semiconductor memory devices withsuitable circuits and functions for the application of the test methodaccording to the present invention.

In a test mode of the semiconductor memory device, it is possible forinstance to reduce the time window for write access in the reference andthus to improve the test severity for the timing of the data strobe anddata signals output by the device under test.

In the same test mode, delay devices fabricated in the semiconductormemory devices themselves may furthermore be connected into the relevantsignal lines.

The delay devices can be made using delay lines, without therebyrestricting the test method according to the present invention or thearrangement according to the present invention to this particularembodiment.

In a particularly preferred embodiment of the present invention, DQS isonly tested close to the application, without further margins. For thispurpose, DQS is delayed using delay device (V) 10 between the deviceunder test and the reference by ¼ of the period duration of CLK or DQS(t_(Clk)/4) with respect to the DQS at the output of the device undertest. In this embodiment of the invention, DQS at the reference is nolonger edge-synchronous with CLK. The length of a simple delay line isabout 0.5 m in this case.

In another embodiment, DQS is delayed by a whole period duration of CLK(t_(Clk)). DQS thus remains edge-synchronous with CLK. Since DQS has tolead the data by ¼t_(Clk), all DQ are delayed by ¾t_(Clk). Adisadvantage compared with the previous embodiment is that all DQ haveto be provided with delay lines, and also the requisite lengths of about1.5 m for DQ and above 2 m for DQS.

In another embodiment, instead of CLK, the inverted clock signal INVCLKis connected to the reference, whereby DQS at the reference has to bedelayed only by ½t_(Clk) and DQ correspondingly has to be delayed onlyby ¼t_(Clk). Compared with the previous embodiment, although the delayline length is reduced, the outlay rises due to the clock signal controlon the test head being no-longer uniform.

A device of the type according to the invention is preferably suitablefor all test apparatuses, designed for testing semiconductor memorydevices without a data strobe terminal.

The foregoing disclosure of the preferred embodiments of the presentinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Many variations andmodifications of the embodiments described herein will be apparent toone of ordinary skill in the art in light of the above disclosure. Thescope of the invention is to be defined only by the claims appendedhereto, and by their equivalents.

Further, in describing representative embodiments of the presentinvention, the specification may have presented the method and/orprocess of the present invention as a particular sequence of steps.However, to the extent that the method or process does not rely on theparticular order of steps set forth herein, the method or process shouldnot be limited to the particular sequence of steps described. As one ofordinary skill in the art would appreciate, other sequences of steps maybe possible. Therefore, the particular order of the steps set forth inthe specification should not be construed as limitations on the claims.In addition, the claims directed to the method and/or process of thepresent invention should not be limited to the performance of theirsteps in the order written, and one skilled in the art can readilyappreciate that the sequences may be varied and still remain within thespirit and scope of the present invention.

1. A test method for a first semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal (DQS) and at least one bidirectional data terminal for data signals (DQ), the method comprising: providing a test apparatus (PA) capable of generating data strobe and data signals and transferring and evaluating data signals in the course of a test using the data strobe and data signals; transferring data from the first semiconductor memory device to a second semiconductor memory device of identical type used as a reference; and evaluating the data after a read-out from the second semiconductor memory device by the test apparatus (PA).
 2. The method of claim 1, further comprising: transferring data from the second semiconductor memory device to the first semiconductor memory device; and evaluating the data after a read-out from the first semiconductor memory device by the test apparatus.
 3. The method of claim 1, wherein the data signals are DQ signals, and wherein the data strobe signal is a DQS signal of a DDR interface in accordance with a JEDEC standard.
 4. The method of claim 1, wherein the second semiconductor memory device is operated in a test mode during the data transfer from the first to the second semiconductor memory device, and wherein a permitted time window for write accesses is reduced during test mode.
 5. The method of claim 1, wherein one of the first and second semiconductor memory devices is operated in a test mode during the data transfer from the first to the second semiconductor memory device and the data strobe signal is delayed in the test mode.
 6. The method of claim 1, wherein a delay device, which delays the data strobe signal by ¼ of the duration of a period of the data strobe signal, is provided in a connection between the data strobe terminals of the first and second semiconductor memory devices.
 7. The method of claim 1, wherein a first delay device is provided in the connection between the data strobe terminals of the first and second semiconductor memory devices, wherein the delay device delays the data strobe signal by the duration of a whole period of the data strobe signal, and wherein second delay devices, which delay the corresponding data signal by ¾ of the period duration of the data strobe signal, are respectively provided in the connections between corresponding data terminals of the first and second semiconductor memory devices.
 8. The method of claim 1, wherein a delay device is provided in the connection between the data strobe terminals of the first and second semiconductor memory devices and said delay device delays the data strobe signal by half the duration of a period of the data strobe signal, wherein connections between corresponding data terminals of the first and second semiconductor memory devices respectively have delay devices that delay the corresponding data signal by ¼ of the period duration of the data strobe signal, and wherein two semiconductor memory devices are connected to mutually inverted clock signals.
 9. The method of claim 1, wherein the first and second semiconductor memory device are DDR-DRAMs or devices that contain DDR-DRAMs.
 10. The method of claim 9, wherein a DDR interface in accordance with a JEDEC standard is situated on the first and second semiconductor memory device.
 11. A device for facilitating measurement of a first semiconductor memory device, which has a bidirectional data strobe terminal and at least one bidirectional data terminal, at a test apparatus that generates data strobe and data signals and transfers and evaluates data signals, the device comprising: a switching device that connects the data strobe and data terminals of the first semiconductor memory device and a second semiconductor memory device respectively either to the test apparatus or via a respective connection to the corresponding terminal of the respective other semiconductor memory device.
 12. The device of claim 11, further comprising: a delay device residing in the connection between the data strobe terminals of the first and second semiconductor memory devices, wherein the delay device delays the data strobe signal by ¼ of the duration of a period of the data strobe signal.
 13. The device of 11, further comprising: a delay device residing in the connection between the data strobe terminals of the first and second semiconductor memory devices, wherein the delay device delays the data strobe signal by the duration of a whole period of the data strobe signal; and delay devices residing in the connections between corresponding data terminals of the first and second semiconductor memory devices, wherein the delay devices delay the corresponding data signal by ¾ of the period duration of the data strobe signal.
 14. The device of claim 11, further comprising: a delay device residing in the connection between the data strobe terminals of the first and second semiconductor memory devices, wherein the delay device delays the data strobe signal by half the duration of a period of the data strobe signal; and delay devices residing in the connections between corresponding data terminals of the first and second semiconductor memory devices, wherein the delay devices delay the corresponding data signal by ¼ of the period duration of the data strobe signal.
 15. The device of claim 11, wherein the first and second semiconductor memory devices are DDR-DRAMs semiconductor memory devices or include semiconductor memory devices.
 16. The device of claim 11, wherein the test apparatus is designed for conventional semiconductor memory devices absent a data strobe terminal. 